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| LSIs for DVD MN85571AC Single-Chip Audio/Video MPEG2 Encoder s Overview The MN85571AC is an audio/video encoder that performs video compression in conformance with the ISO/IEC 13818-2 (MPEG2 video) and ISO/IEC 11172-2 (MPEG1 video) standards and audio compression in conformance with the Dolby Digital * system. It also can multiplex the compressed audio and video signals. Note) 1. *: Dolby Digital is a registered trademark of Dolby Laboratories. Neither the supply of this product that implements Dolby technologies nor the use of this product in end user products or other end products implies the recognition of any implicit rights or licenses based on patents or other intellectual property belonging to Dolby Laboratories. Licenses to use this product must be acquired from Dolby Laboratories. 2. Use of this product in MPEG2-related products requires patent licenses from the following company. MPEG LA, LLC 250 Steel Street, Denver, Colorado USA 80206 s Features * Video encoding * Image compression technique: Compression in conformance with the ISO/IEC 13818-2 (MPEG2 video) and ISO/ IEC 11172-2 (MPEG1 video) standards * Generation of image sizes for the DVD video recording standards from ITU-R BT.656 (D1 parallel input) conforming signals * Functions for conversion of horizontal and vertical resolutions. * Special quantization processing and filtering (time, horizontal, and vertical axes) * Audio encoding * Encoding techniques: Dolby Digital and linear PCM * Sampling frequency: 48 kHz * Number of channels: 2 channels (left and right) * Digital input interface: One system (supports both master and slave mode operation) * External components * External host for initialization and user-specific settings, and buffer memories (One 32-bit 64M SDRAM or two 16) * Power supply system: Two supply voltages: 3.3 V (I/O supply voltage and internal PLL circuit supply voltage), 1.8 V (internal circuit supply voltage) s Applications * Used in the encoder block in AV recording equipment that uses the MPEG2 technique, such as DVD recorders. Publication date: January 2002 SDD00023AEM 1 MN85571AC s Block Diagram The MN85571AC consists of the 5 blocks listed below. 1. Video encoder block. This block is based on the MN85560 MPEG2 video encoder, but provides additional functionality as well. 2. Audio encoder block. This block is based on the MN67735JA Dolby Digital encoder core. 3. Multiplexer block. This block multiplexes the encoded video and audio data. 4. SDRAM interface block (MIF). This block handles data exchange with external SDRAM. 5. Host interface block (HIF). This block handles data exchange with and accepts control commands from an external host. SDRAM control signal MCLKIN (108 MHz) MCLK MDQ 32 4. MIF MA 14 ADIN PCKI PCKO LRCKIO BCKIO AMAS SCLK (27 MHz) 2. Audio encoder block DSP 36 MHz ASF CBUS ABUS 3. Multiplexer 8 block CIF PLL 108 MHz SYSENC CDO RMRS HCIFZ RCLKO RCLKI CDACK CDREADY IPIC VOB VIF PRE ME1 ME2 MSP DCTQ VLC VIN VCLK (27 MHz) 8 1. Video encoder block SRISC DIF ERISC Startup Startup 5. HIF 16 HD 2 SDD00023AEM Note) The MN85571AC includes two RISC microcontrollers (for video encoding and data multiplexing) and one DSP for audio encoding. The microcode for these two RISC microcontrollers must be downloaded to the on-chip instruction memory before the MN85571AC is used. The DSP microcode is stored in on-chip ROM, and does not need to be downloaded. control signal MN85571AC s Internal Resource Mapping The MN85571AC has two types of internal resources that are accessed by the external host with different methods. 1) Direct addressing resources (registers only) These resources are mainly used for controlling this device and indicating the internal state of the device. These are 16-bit registers. 2) Indirect addressing resources (registers and memory) These are memory and other resources that mainly consist of parameter setting registers used at initialization and memory that holds microcode. 1. Direct addressing resources These are accessed by specifying the address to the external pins HA[3:0]. Table 1 shows the address mapping for the direct addressing resources. Table 1. Direct Addressing Register Mapping HA[3 : 0] %0000 %0001 %0010 %0011 %0100 %0101 %0110 %0111 %1000 %1001 %1010 %1011 %1100 %1101 %1110 %1111 Register CHIPCTL0 Reserved CHIPST0 CHIPST1 STMSK Reserved INADR0 Reserved INDAT0 Reserved DIFACC DIFPTR DIFDAT Reserved DMAACC Reserved r DMA access register r/w r/w r/w DIF access register DIF access address register DIF access data register r/w Indirect access data register r/w Indirect access address register r r r/w Status register 0 (interrupt) Status register 1 (mode, busy) Status report signal mask register r/w r/w Function Control signal register 0 (reset, mode, srisc en) Note) 1. CHIPCTL0 is only reset by a hardware reset (setting the external pin NRST low). 2. Chip operation is not guaranteed after access to any of the reserved direct addressing registers. 3. The symbols r and w indicate read and write as seen from the external host. The symbol r alone indicates a read-only register, and r/w indicates the both read and write are possible. 4. Accesses to registers other than CHIPCTL0 are invalid in the reset state (software reset). All register accesses are invalid in the hardware reset state. 5. The CHIPCTL0, CHIPST0, CHIPST1, STMASK, INADR0, and DIFPTR registers can all be read in the hold, slave, and run states. SDD00023AEM 3 MN85571AC s Internal Resource Mapping (continued) 2. Indirect addressing resources (registers and initial load memory) These internal resources are accessed by storing the address of the indirect addressing resource in the INADR0 indirect access address register and reading or writing the INDAT0 indirect access data register. Other than the registers used for communication with the external host and the SRISC, these resources can only be accessed in the slave state. While these resources have a structure that consists of 16 bits per address, indirect addressing access writes must be performed in 32-bit units. Tables 2 and 3 show the address maps. Table 2. Indirect Addressing Resources Address Map Overview indir adr *1 $0000 - $01FF $0200 - $03FF $0400 - $05FF $0600 - $0FFF $1000 - $17FF $1800 - $3FFF $4000 - $7FFF $8000 - $8FFF $9000 - $9FFF $A000 - $CFFF $D000 - $FFFF Description Communication registers, parameter registers, and other registers Video input intensity conversion data memory (ITDM) A: 256 words x 8 bits *2 Video input intensity conversion data memory (ITDM) A: 256 words x 8 bits *2 Reserved Video encoding block RISC data memory (VDM): 1K words x 16 bits *2 Reserved Video encoding block RISC instruction memory (VIRAM): 8K words x 32 bits Reserved Multiplexing block RISC data memory (SDM): 2K words x 16 bits *2 Multiplexing block RISC instruction memory (SIRAM): 6K words x 24 bits 24 bits Reserved Note) *1: The notation indir adr indicates the value stored in the INADR0 indirect access address register when accessing an indirect addressing resource. *2: Data only exists at even addresses. Table 3. Indirect Addressing Resources (Registers) Address Map indir adr * $0000 - $000F $0010 - $0013 $0014 $0015 - $001F $0020 $0021 $0022 - $0025 $0026 - $01FF Description External host/SRIC communication register Reserved Video input block parameter register Reserved DMA data I/O block parameter register Reserved Code output block parameter register Reserved cifreg difreg vifreg Name hifreg Run/Hold q x x x x x x x Slave x x W x W x W x Note) 1. *: The notation indir adr indicates the value stored in the INADR0 indirect access address register when accessing an indirect addressing resource. 2. q: Both read and write access allowed. W: Write access allowed (Cannot be read.) x: No access is allowed. Chip operation is not guaranteed if registers for which access is only allowed in the slave state are accessed in either the run or hold states. Chip operation is not guaranteed if areas indicated as reserved are accessed. 4 SDD00023AEM MN85571AC s Pin Arrangement GND MCKE MDQ19 MDQ18 3.3V-VDD MDQ17 MDQ16 GND 1.8V-VDD MDQ15 MDQ14 3.3V-VDD MDQ13 MDQ12 GND MDQ11 MDQ10 3.3V-VDD MDQ9 MDQ8 1.8V-VDD GND MDQ7 MDQ6 3.3V-VDD MDQ5 MDQ4 GND MDQ3 MDQ2 3.3V-VDD MDQ1 MDQ0 1.8V-VDD GND 3.3V-VDD DMACLK GND NHCS 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 NHWE NHRE 1.8V-VDD 3.3V-VDD HA3 HA2 HA1 HA0 GND HCFZ GND MDQ20 MDQ21 3.3V-VDD MDQ22 MDQ23 1.8V-VDD GND MDQ24 MDQ25 3.3V-VDD MDQ26 MDQ27 GND MDQM 3.3V-VDD NMWE GND 1.8V-VDD NMCS GND MCLKIN GND NMRAS 3.3V-VDD NMCAS GND MCLK 3.3V-VDD MDQ28 MDQ29 1.8V-VDD GND MDQ30 MDQ31 3.3V-VDD MA0 MA1 GND MA2 MA3 1.8V-VDD 3.3V-VDD MA4 MA5 GND MA6 MA7 3.3V-VDD MA8 MA9 GND 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 GND HD15 HD14 HD13 3.3V-VDD HD12 HD11 HD10 1.8V-VDD GND HD9 HD8 HD7 3.3V-VDD HD6 HD5 HD4 GND HD3 HD2 1.8V-VDD 3.3V-VDD HD1 HD0 NHDACK GND NHDREQ NHINT BUSY 3.3V-VDD NRST CDO7 CDO6 1.8V-VDD GND CDO5 CDO4 CDO3 3.3V-VDD CDO2 CDO1 CDO0 GND CDREADY VOB 1.8V-VDD IPIC 3.3V-VDD RCLKI RMRS CDACK GND GND MA10 MA11 3.3V-VDD MA12 MA13 1.8V-VDD GND TRST N.C. 3.3V-VDD VCLK GND VIN0 VIN1 1.8V-VDD VIN2 VIN3 3.3V-VDD VIN4 VIN5 VIN6 VIN7 GND AGND N.C. AVDD GND 1.8V-VDD SCLK 3.3V-VDD PCKI 3.3 V (TOPVIEW) Note) The same signal must be input to both the NRST and TRST pins. 3.3 V 1.8V-VDD BCKO 3.3V-VDD PCKO GND LRCKO 3.3V-VDD RCLKO GND AMAS ADIN GND SDD00023AEM 5 MN85571AC s Signal and Control Timing * Signal Overview The MN85571AC I/O signals can be classified by function as shown below. See the Pin Descriptions section for details on these signals. All signal pins conform to the LVTTL standard. Clock SCLK NRST TRST BUSY VCLK VIN[7:0] Control Video I/F RMRS RCLKI RCLKO CDO[7:0] CDREADY CDACK IPIC VOB HCIFZ MCLK MCLKIN MCKE NMCS NMRAS NMCAS NMWE MDQM MA[13:0] MDQ[31:0] AGND AVDD (For 3.3 V PLL) Code I/F Host I/F HA[3:0] HD[15:0] NHCS NHRE NHWE NHINT DMACLK NHDACK NHDREQ SDRAM I/F Audio I/F ADIN PCKI PCKO BCKIO LRCKIO AMAS 208-pin GND 1.8V-VDD 3.3V-VDD Power 6 SDD00023AEM MN85571AC s Pin Descriptions Type Clock Control Control Control Video I/F Video I/F Host I/F Host I/F Host I/F Host I/F Host I/F Host I/F Host I/F Host I/F Host I/F Audio I/F Audio I/F Audio I/F Audio I/F Audio I/F Audio I/F Code I/F Code I/F Code I/F Code I/F Code I/F Code I/F Code I/F Code I/F Code I/F SDRAM I/F SDRAM I/F SDRAM I/F SDRAM I/F SDRAM I/F SDRAM I/F Pin Name SCLK NRST TRST BUSY VCLK VIN[7:0] HA[3:0] HD[15:0] NHCS NHRE NHWE NHINT DMACLK NHDACK NHDREQ ADIN PCKI PCKO BCKIO LRCKIO AMAS RMRS RCLKI RCLKO CDO[7:0] CDREADY CDACK IPIC VOB HCIFZ MCLK MCLKIN MCKE NMCS NMRAS NMCAS I/O I I I O I I I I/O I I I O I I O I I O I/O I/O I I I O O O I O O I O I O O O O System clock input Chip initialization reset input signal 1 Chip initialization reset input signal 2 Chip status output signal Video data input clock Video data input signal Host interface address signal Host interface data I/O Host interface chip select signal Host interface read enable signal Host interface write enable signal Host interface interrupt occurrence report signal DMA I/O block 1 bus mode clock input Code output enable signal (DMA mode) DMA transfer request signal PCM data input (audio data input) PCM master clock input PCM master clock output Bit clock (64 fs or 32 fs) I/O (pulled up) Left/right channel discrimination clock (fs) I/O (pulled up) Master mode/slave mode switching control RCLK clock I/O switching Code output clock input (Used in RSLAVE mode, pulled up.) Code output clock output (Used in RMASTER mode.) Serial code output signal Serial code output ready signal Serial code output request signal Pack flag that includes the VOBU start I Picture VOB start pack flag Code output pin initial state control External memory (SDRAM) clock output Clock input for data transfer between external memory and this product External memory (SDRAM) CKE output External memory (SDRAM) chip select output External memory (SDRAM) RAS output External memory (SDRAM) CAS output Description SDD00023AEM 7 MN85571AC s Pin Descriptions (continued) Type SDRAM I/F SDRAM I/F SDRAM I/F SDRAM I/F Power Power Power Power Power Pin Name NMWE MDQM MA[13:0] MDQ[31:0] AVDD AGND 3.3V-VDD 1.8V-VDD GND I/O O O O I/O I I I I I Description External memory (SDRAM) write enable output External memory (SDRAM) data output buffer control External memory (SDRAM) address output External memory (SDRAM) data I/O (pulled up) PLL system power supply (3.3 V) PLL system ground 3.3 V system power supply 1.8 V system power supply Ground 8 SDD00023AEM MN85571AC s Electrical Characteristics 1. Absolute Maximum Ratings Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Input voltage Output voltage Average output current Power dissipation Operating temperature Storage temperature Symbol 3.3V-VDD 1.8V-VDD AVDD VI VO IO PD Topr Tstg Rating - 0.3 to +4.6 - 0.3 to +2.5 - 0.3 to +4.6 - 0.3 to 3.3 V-VDD + 0.3 (Upper limit: 4.6) - 0.3 to 3.3 V-VDD + 0.3 (Upper limit: 4.6) 24 2.3 (4 layers) 0 to +70 -40 to +125 Unit V V V V V mA W C C Note) 1. The absolute maximum ratings are limit values for stresses applied to the chip so that the chip will not be destroyed. Operation is not guaranteed within these ranges. 2. All of the 3.3 V VDD pins, 1.8 V VDD pins, and VSS pins must be connected externally to the 3.3 V power supply, 1.8 V power supply, and ground, respectively. 3. Connect bypass capacitors (at least 0.1 F) between the 3.3 V VDD and VSS pins, between the 1.8 V VDD and VSS pins, and between the AVDD and VSS pins. 4. The power supply voltages must be applied in the following order: first apply the 3.3 V system level (3.3V-VDD, AVDD), and then apply the 1.8 V system level (1.8V-VDD). When removing power from this IC, first remove the 1.8 V system level (1.8V-VDD) and then remove the 3.3 V system level (3.3V-VDD, AVDD). 2. Recommended Operating Conditions at VSS = 0 V, AVSS = 0 V Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Ambient temperature System clock frequency Symbol 3.3V-VDD 1.8V-VDD AVDD Ta SCLK 3.3V-VDD = 3.0 V to 3.6 V AVDD = 3.0 V to 3.6 V DUTY: 50%10% Jitter: 50 ppm *1 3.3V-VDD = 3.0 V to 3.6 V DUTY: 50%10% Jitter: 50 ppm *1 3.3V-VDD = 3.0 V to 3.6 V DUTY: 50%10% 3.3V-VDD = 3.0 V to 3.6 V DUTY: 50%10% 3.3V-VDD = 3.0 V to 3.6 V DUTY: 50%10% Conditions Min 3.0 1.65 3.0 0 Typ 3.3 1.80 3.3 Max 3.6 1.95 3.6 70 27.0 Unit V V V C MHz Video data input clock frequency Code data output clock frequency *2 DMA transfer clock frequency PCM master clock frequency VCLK 27.0 MHz RCLKI DMACLK PCKI 33.0 33.0 18.432 MHz MHz MHz Note) *1: When TS output is used, the PCR counter SCLK and VCLK jitter must be held within 30 ppm as stipulated by the ISO/ IEC 13818-1 standard. *2: The value shown for RCLKI is the stipulated value for forward clock input standalone mode. The maximum value for reverse clock input standalone mode is 16 MHz. SDD00023AEM 9 MN85571AC s Interfaces 1. Host interface Accesses to this product's internal resources from an external host take place using the host interface block (HIF). There are two techniques for accessing resources over the host interface as follows. 1) Direct addressing access 2) Indirect addressing access 1) Direct addressing access [Read] * Timing chart trcyc Valid Data HA[3:0] tcsda tcsgat NHCS tadcs treda NHRE tadre tregat HD[15:0] "Hi-Z" tcsad tcsdhd tread tdhd Valid Data "Hi-Z" NHWE "H" * AC Characteristics Item Read cycle time HA[3:0] setup time from the NHCS falling edge HA[3:0] setup time from the NHRE falling edge HD[15:0] bus drive start time from the NHCS falling edge HD[15:0] bus drive start time from the NHRE falling edge HD[15:0] valid data output time from the NHCS falling edge HD[15:0] valid data output time from the NHRE falling edge HA[3:0] hold time from the NHCS rising edge HA[3:0] hold time from the NHRE rising edge HD[15:0] valid data hold time from the NHCS rising edge HD[15:0] valid data hold time from the NHRE rising edge Symbol Min trcyc tadcs tadre tcsgat tregat tcsda treda tcsad tread tcsdhd tdhd 200 0 0 40 40 2 2 Typ Max 2 2 135 135 Unit ns ns ns ns ns ns ns ns ns ns ns 10 SDD00023AEM MN85571AC s Interfaces (continued) 1. Host interface (continued) 1) Direct addressing access (continued) [Write] * Timing chart twcyc Valid Data HA[3:0] twadcs twcsad NHCS tadwe twecs twead NHWE tweset twdhd HD[15:0] "Hi-Z" Valid Data "Hi-Z" NHRE "H" * AC Characteristics Item Write cycle time HA[3:0] setup time from the NHCS falling edge HA[3:0] setup time from the NHRE falling edge HD[15:0] valid data setup time from the NHWE rising edge HA[3:0] hold time from the NHCS rising edge HA[3:0] hold time from the NHWE rising edge NHCS rising edge time from NHWE rising edge HD[15:0] valid data hold time from the NHWE rising edge Symbol Min twcyc twadcs tadwe tweset twcsad twead twecs twdhd 200 0 0 20 40 40 0 1 Typ Max Unit ns ns ns ns ns ns ns ns SDD00023AEM 11 MN85571AC s Interfaces (continued) 1. Host interface (continued) 2) Indirect addressing access [Read] (1) The indirect address value is written to INADR0 (HA[3:0] = $6). This sets the indirect address. (2) Data is read from INDAT0 (HA[3:0] = $8). At this time the data at the address set in INADR0 is read out over this device's internal bus, although it appears to be read out from INDAT0. This completes the read operation. At the same time, the value stored in INADR0 is automatically incremented (auto increment). Write to INADR0 Read from INDAT0 HA[3:0] NHCS NHWE NHRE HD[15:0] HA[3:0] = $6 HA[3:0] = $8 Address Read Data The value in INADR0 is incremented and now points to . [Write] (1) The indirect address value is written to INADR0 (HA[3:0] = $6). This sets the indirect address. (Since writes are performed in 32-bit units, the set indirect address must be an even value.) (2) Data is written to INDAT0 (HA[3:0] = $8). This latches the lower 16 bits of the data. (3) Another data is written to INDAT0 (HA[3:0] = $8). This, in conjunction with the 16 bits of data acquired in step (2) above, forms a 32-bit data unit, which is then written over the internal data bus. At the same time, the value stored in INADR0 is automatically incremented by 2 (auto increment). Write to INADR0 Write to INADR0 Write to INADR0 HA[3:0] NHCS NHWE NHRE HD[15:0] HA[3:0] = $6 HA[3:0] = $8 HA[3:0] = $8 "H" Address Data[15:0] Data[31:16] The data (Data[31:0]) is written and INADR0 is incremented by 2. INADR0 now points to . 12 SDD00023AEM MN85571AC s Interfaces (continued) 2. DMA transfer interface (DIF) The DMA transfer interface (DIF) transfers data using DMA between the external host and this device's DMA data transfer buffer memory (WRDM). Since WRDM has a size of 1 024 32-bit words, the maximum valid data count is 2 048. (This function is valid when the CHIPCTL0 direct addressing access register dmasel bit is 0.) The WRDM can be accessed in two ways: by read or write instructions from the SRISC and by DMA data transfers (read or write) from the external host. Since there are two techniques, which technique gains access is arbitrated by the DIF internal arbitration circuit. Access requests to the arbitration circuit are issued from the SRISC by instruction execution, and from the external host by writing a 1 to the DIFACC (HA[3:0] = $A) req register (a direct addressing register). If requests are issued to the arbitration circuit at the same time, access permission is granted according to the priority determined by the value of the difreg ($0020) indirect addressing access register. Note that there are two DMA transfer modes: "single bus cycle DMA transfer mode", in which access is synchronized with the DMA clock signal (DMACLK), and "two bus cycle DMA transfer mode", in which transfers are not dependent on a clock signal. 3. Code output interface The code output interface is provided to transfer data to a communication system or to the storage system media and outputs a multiplexed AV bit stream to external circuits. There are two major classes of output formats provided by the code output interface: "standalone mode (8-bit parallel)", which outputs the bit stream using a dedicated set of pins, and "DMA transfer mode (16-bit parallel) which outputs using an external host bus shared with the host interface. The setting of the CHIPCTL0 dma sel register (a direct addressing register) selects which of these two output formats is used. If this bit is set to 0, standalone mode is used, and if set to 1, DMA transfer mode is used. Additionally, there are three clock modes in standalone mode. These consist of two modes that use a code output clock (RCLKI) input to this device, "inverted clock input standalone mode", and "noninverted clock input standalone mode as well as a mode that uses a code output clock (RCLKO) output from this device, "ARIB parallel interface standard mode (TS output)". Also note that there are two DMA transfer modes which differ in the number of bus cycles required to transfer data, "single bus cycle DMA transfer mode" and "two bus cycle DMA transfer mode". The table below summarizes these modes, and lists the clock frequencies, pins, and other items used in each mode. Note that in every one of these modes, the maximum amount of valid output data per single handshake operation is 2 048 bytes, and that the maximum average output bit rate is 15 Mbps. Mode Standalone mode Inverted/noninverted clock input ARIB parallel interface standard DMA transfer mode Single bus cycle Two bus cycle Pin names used CDO[7:0], CDREADY, CDACK, RCLKI, (IPIC, VOB)3 CDO[7:0], CDREADY, RCLKI, IPIC, (VOB)3 HD[15:0], NHDREQ, NHDACK, DMACLK HD[15:0], NHCS, HA[3:0], NHRE, NHWE, NHDREQ Clock frequencies RCLKI 16 MHz maximum RCLKO 6.75 MHz, 3.375 MHz DMACLK 33 MHz maximum Clock signal not required Output data format MSB first MSB first Big Endian/ Little Endian Big Endian/ Little Endian SDD00023AEM 13 MN85571AC s Interfaces (continued) 4. Video data input interface * Interface pin descriptions Pin Name VIN[7:0] I/O I Description Video data input Video data must be input in synchronization with the video data input clock (VCLK). The format of the input video data must be ITU-R VCLK I BT.656 (level D1, 4:2:2). Video data input clock input The video data input to this product assumes that the input signal has been time base corrected (TBC) in the stage prior to this product. This product also assumes that the PCM data input and the video data input are locked in the stage prior to this product. 5. PCM data input (audio data input) interface The PCM data input interface is provided for input of the audio data (PCM coded data) to the audio encoding block. This product performs encoding for audio data that is sampled at a sampling frequency of 48 kHz. It uses either Dolby Digital or linear PCM as the encoding technique. There are limitations on the PCM data input quantization word length depending on the encoding technique used. For Dolby Digital processing, this product supports 16, 18, 20, and 24-bit quantizations. For linear PCM processing it only supports 16-bit quantization. This product supports 2-channel (left/right) audio, and data is 1-bit serial data transmitted MSB first. This product supports the I2S, left justified, and right justified formats as input formats. The PCM data input interface can be switched between two modes: master mode and slave mode. In master mode, a PCM master clock signal (256 or 384 fs) is input to this product's PCKI pin and used to create the output PCM master clock output signal, the bit clock signal, and the left/right channel discrimination clock signal for the external A/D converter. These signals are output from the PCKO, BCKIO, and LRCKIO pins, respectively. In slave mode, the PCKI, BCKIO, and LRCKIO pins are used to input a PCM master clock signal (256 or 384 fs), bit clock signal, and a left/right channel discrimination clock signal, respectively. (In this mode, the PCKO pin must be left open (N.C.).) All the PCM data input interface parameter settings are set from multiplexing block SRISC microcode. * Interface pin descriptions Pin Name BCKIO LRCKIO ADIN PCKI PCKO I/O I/O I/O I I O Bit clock output Left/right channel discrimination clock output PCM data (audio data) input PCM master clock input PCM master clock output Description 14 SDD00023AEM MN85571AC s Interfaces (continued) 6. SDRAM interface This product's SDRAM interface supports JEDEC standard single data rate SDRAM with a CAS latency of 3, a cycle time of 8 ns or faster, and an access time of 6 ns or faster. Data is transferred in 32-bit units, and either one 64M 32-bit data path SDRAM chip or two 64M 16-bit data path SDRAM chips may be used. * Pin Descriptions Pin Name MCLK MCLKIN NMCS NMRAS NMCAS NMWE MDQM MA[13 : 0] MDQ[31 : 0] MCKE I/O O I O O O O O O I/O O External memory clock output Clock input for data transfers between external memory and this product External memory chip select output External memory RAS output External memory CAS output External memory write enable output External memory data output buffer control External memory address output External memory data I/O (These pins have built-in pull-up resistors.) External memory CKE output Description s Package Dimensions (Unit: mm) * LQFP208-P-2828 (Lead-free package) 30.000.20 28.000.10 156 157 105 104 (1.25) 53 1 52 208 1.70 max. 0.150.05 0.08 M 1.400.10 (1.25) 0.50 28.000.10 30.000.20 0.200.05 (1.00) Seating plane 0.10 0.100.10 0 to 8 0.500.20 SDD00023AEM 15 Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company. Please read the following notes before using the datasheets A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited. 2001 MAR |
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